1. Field of the Invention
The present disclosure relates to a semiconductor device, and more particularly to a group III nitride semiconductor device which can be used as a power transistor.
2. Description of the Related Art
A group III nitride semiconductor represented by GaN or AlGaN has wide bandgap, and high breakdown voltage. Furthermore, with the group III nitride semiconductor, a hetero structure such as AlGaN/GaN layers can be readily formed, and a high-concentration electron channel (two-dimensional electron gas which is referred to as 2DEG below) is generated in the GaN layer near an interface of the AlGaN/GaN layers due to piezoelectric charges generated from a difference in lattice constant between the AlGaN and the GaN layers, and a difference in bandgap between the AlGaN and the GaN layers. Thus, in an electron device using the group III nitride semiconductor, a large-current operation and a high-speed operation can be performed. As a result, the group III nitride semiconductor can be expected to be used in an electron device such as a power field effect transistor (FET) and a diode.
In addition, since a large-diameter free-standing GaN substrate has not been available before, an epitaxial substrate formed on a SiC, sapphire, or Si substrate has been used in a lateral AlGaN/GaN-HFET in general. However, the large-diameter free-standing GaN substrate has been recently put into practical use, so that a vertical GaN-FET starts to draw attention because a chip size can be miniaturized, and costs can be reduced.
As one example of the vertical GaN-FET, FIG. 1 shows a cross-sectional structure of a vertical HFET made of compound semiconductor disclosed in Unexamined Japanese Patent Publication No. 2010-97974. Channel layer 2 (made of i-GaN) is formed on appropriate substrate 1 (made of n-GaN), and carrier supply layer 6 (made of AlGaN) having a bandgap greater than channel layer 2 is formed along channel layer 2. Thus, 2DEG layer 7 is generated due to a difference in bandgap between carrier supply layer 6 and channel layer 2. Insulating layer 11, gate electrode 10, insulating layer 11 are sequentially formed from a bottom, on substrate 1 along carrier supply layer 6. In addition, electrode 8 (a drain or source) is formed on a bottom surface and makes an ohmic contact with substrate 1, and electrode 9 (drain or source) is formed on upper surfaces of channel layer 2 and carrier supply layer 6 and makes an ohmic contact with 2DEG layer 7. Gate electrode 10 makes a Schottky contact with carrier supply layer 6.
Regarding an operation of the vertical HFET, a voltage is applied to electrode 10 to form a depletion layer (not shown) across a Schottky barrier, whereby a current in 2DEG layer 7 is controlled. Thus, a current between ohmic-contacting electrode 8 and ohmic-contacting electrode 9 is controlled. The FET in which the 2DEG channel is controlled is generally called a high electron mobility transistor (HEMT). According to this structure disclosed in the Unexamined Japanese Patent Publication No. 2010-97974, since a gate length is defined as a thickness of gate electrode 10, a short gate can be readily manufactured, so that a high-speed operation can be performed.